As dimensions and feature sizes of semiconductor integrated circuits (ICs) are scaled down, the density of the elements forming the ICs is increased and the spacing between elements is reduced. Such spacing reductions are limited by light diffraction of photo-lithography, mask alignment, isolation and device performance among other factors. As the distance between any two adjacent conductive features decreases, the resulting capacitance increases, which will increase power consumption and time delay.
To reduce parasitic capacitance and correspondingly improve device performance, IC designers utilize low-k dielectrics. One kind of low-k material is produced by creating large voids or pores in a dielectric. Voids can have a dielectric constant of nearly 1, thereby reducing the overall dielectric constant of the porous material by increasing the porosity of the material. Large pores, also referred to as air gaps, can provide an extremely low-k dielectric between the two conductive features.